Concerning the composition of a semiconductor integrated circuit device, there is known in the art a circuit of a master slice type, previously called a gate array or an embedded array, in which CMOS transistors are formed in a semiconductor device formation layer, then a wiring layer is laid on the semiconductor device formation layer, and then power and signal lines are wired on the wiring layer.
Concerning the composition of a CMOS gate array LSI, a basic cell in which combining a pair of PMOSs and a pair of NMOSs, as described in JPB59-25381, is well known. However, in the case of this basic cell, when constituting a memory circuit, the transistor size is large and the area occupied by memory cells becomes wide.
Additionally, as described in JPA59-150446 and JPA61-268040, there is presented a basic cell constructed by four PMOSs and four NMOSs. However, developing these basic cells into various different kinds of logic gates is difficult.
In order to solve these problems, a small transistor size (FIG. 20) having a contact hole on both sides of the power line, documented in the IEEE 1992 ASIC conference (September, 1992), has been proposed.
However, in the prior art, a memory cell circuit based on an SRAM is constructed; and alternatively, in the case of constructing a complicated macro-cell, like a flip-flop, occupied area becomes large, and channels used in making logic are reduced, and these lead to wire extrusion of the metal wiring of the first layer surface and the second layer surface; and the channel wiring needed for connecting logic circuitry is eradicated. For this purpose, if the metal wiring is automatically wired, unconnected wiring results at various locations, and the utilization factor is lowered.
The first object of the present invention is to provide a semiconductor integrated circuit device, made up of a master slice type LSI of gate array and/or embedded array type having compatible gate speed and memory density as well as having high operational efficiency.
The typical prior art static type RAM memory cell is composed of a latch circuit, in which input and output are alternately connected, and a transfer gate MOSFET, situated between a pair of input/output nodes and a complementary data line, for the address selection purpose. For this kind of memory cell, in a situation of a storage voltage remaining in the complementary data line to which numerous memory cells are commonly connected, if the word line is at the selection level, a write-in error flows into the memory cell. For this reason, a pre-charge of the complementary data line is executed by the clock signal for the synchronized static type RAM and by the timing signal produced by the address signal transform detector circuit (ATD) for the asynchronous static type RAM. A Japanese patent, JPA60-32199, for instance, describes these kinds of static type RAM.
In the above synchronous type, there is a need to set the pre-charge time duration; and in the asynchronous type, because of the countermeasure for the skew of address and the necessity for pulse width maintenance and pulse width fitting for the pre-charge time duration, the reduction of memory cycle or, in other words, the speed-up of memory access is prevented.
In order to solve these problems, the second object of the present invention is to provide a semiconductor integrated circuit device which has realized a reduction of memory cycle through a simplified static type RAM structure.
Further objects and novel features of the present invention as well as those presented above will become apparent from a consideration of the ensuing description and drawings.